1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and, more particularly, to a repair circuit, a memory apparatus using the same and an operating method thereof.
2. Related Art
In general, a memory apparatus may include a plurality of memory banks each of which includes a plurality of memory cell arrays. In each memory bank, a plurality of word lines and a plurality of bit lines may be disposed perpendicular to each other, and memory cells may be coupled at points where the word lines and the bit lines intersect. As the manufacturing process of a memory apparatus is highly integrated, a failure may occur due to a coupling relationship between memory cells or between a memory cell and a word line or a bit line. Therefore, a memory bank includes a redundant array for replacing a memory cell in which a failure occurs.
FIG. 1 is a diagram schematically illustrating a representation of an example configuration of a memory apparatus 10 according to the conventional art. In FIG. 1, the memory apparatus 10 may include a first memory bank MB1, a second memory bank MB2, and a row decoder and repair circuit 11. Each of the first memory bank MB1 and the second memory bank MB2 may include a plurality of word lines WL. Further, each of the first memory bank MB1 and the second memory bank MB2 may include a normal array NA and a redundant array RA. The number of the word lines disposed in the normal array NA may be larger than the number of the word lines disposed in the redundant array RA. The row decoder and repair circuit 11 may be disposed between the first and second memory banks MB1 and MB2, and select any bank of the first and second memory banks MB1 and MB2 and any word line in the selected memory bank, based on an address signal. The row decoder and repair circuit 11 may include a fuse circuit for replacing a failed word line with a redundant word line disposed in the redundant array RA, when a failure occurs in the word line selected based on the address signal.
It is illustrated in FIG. 1 that four word lines are disposed in the redundant array RA of each memory bank. Also, it is illustrated that failures have occurred in five word lines in the normal array NA of the first memory bank MB1 and failures have occurred in three word lines in the normal array NA of the second memory bank MB2. The symbol X appearing on the failed memory cell and/or word line represents a failure that occurred in a memory cell and/or word line. In the second memory bank MB2, the three word lines in which failures have occurred may be replaced with the word lines disposed in the redundant array RA. Therefore, the second memory bank MB2 may operate normally. However, in the first memory bank MB1, because the number of failed word lines is larger than the number of the word lines disposed in the redundant array RA, one among the five failed word lines may not be replaced. Accordingly, the failure of the one word line may not be repaired. Due to this fact, the first memory bank MB1 may not operate normally, and as a result, the entire memory apparatus 10 cannot help but be sorted out as a bad product.